Benjamin Fletcher – CHERI Alliance
Over the last few months I’ve had the pleasure of working with members of the CHERI Alliance’s CHERI-in-SoC Working Group to put together the first version of the CHERI Tag Bit Transport Overlay Standard.
One of the challenges of building a CHERI-enabled SoC is that capabilities don’t just consist of the data you can see in memory. They also have an associated tag bit, which needs to make its way safely through the system alongside that data.
If we want CHERI systems to be built successfully from components supplied by different companies, we need to agree on how that works. This standard is intended to do exactly that: define a common way of transporting CHERI tag bits through an SoC, including mappings for widely used protocols such as AXI and CHI.
We’ve now published version 0.9 of the standard. The reason it is version 0.9 is important: this isn’t intended to be the final word. We’d really like people building CHERI systems, interconnects and IP to read it, try to break it, and tell us what we’ve missed.
It’s been a great experience putting this together with the members of the working group. There have been lots of interesting discussions along the way, and the standard is considerably better as a result.
Please have a read, and let us know what you think. If you’d like to learn more about our working group – or even join – do let me know. We still have lots to do!