Codasip has added built-in, fine-grained memory protection to its RISC-V processors by extending the RISC-V ISA with CHERI-based custom instructions. The company announced the availability of CHERI in their 700 processor family in October 2023. This is the first commercial implementation of CHERI available for licensing. The company has committed to making CHERI available in all its new cores. As a founding member of RISC-V International, Codasip chair and actively contribute to several technical working groups, including security and safety topics of interest, and are active members in the CHERI Special Interest Group. In 2024, Codasip CHERI technology was awarded the prestigious Embedded Award at the Embedded World Conference in Nuremberg, Germany. In collaboration with other CHERI Alliance members, Codasip has built a CHERI SDK on existing open-source projects, and has donated it to the CHERI Alliance for unrestricted use by everyone implementing CHERI on RISC-V.
